RF Bipolar Transistors: What They Are and How to Select Them for Microwave Circuits

Updated

RF bipolar transistors are NPN or PNP junction devices optimized for signal amplification or power generation at radio and microwave frequencies, rather than for switching or low-frequency analog work. Choose them when you need high gain per stage, low phase noise, or a proven, well-characterized die for a hybrid MIC; choose LDMOS or other FETs when you need higher breakdown voltage, simpler biasing, or high power at lower frequencies. The selection criteria below apply to both packaged parts and bare-die devices of the kind US Microwaves lists under its RF power transistors and bare-die products.

What "RF bipolar" means in practice

An RF bipolar transistor is a BJT whose geometry, doping profile, and package (or die layout) are designed so that current gain and power gain hold up into the hundreds of MHz to several GHz. Compared with a general-purpose BJT, the RF version trades ruggedness and low-frequency beta for:

  • Higher fT/fmax — thinner base, smaller emitter stripes, lower parasitics.
  • Controlled input/output impedance — often specified as S-parameters at a reference plane.
  • Thermal paths designed for the die — critical for power devices and for bare-die MIC assembly.

In a thin-film MIC flow, the bipolar is typically a bare die mounted on a carrier or submount, with matching networks built from spiral chip inductors, ceramic or MOS/MNOS capacitors, and thin-film resistors on the same substrate.

RF bipolar vs. LDMOS and other RF power devices

Criterion RF bipolar (BJT) LDMOS Notes
Control Current-driven; needs base current and bias network Voltage-driven; gate bias only Bipolar bias networks are more complex and must be temperature-stable
Gain per stage Generally high at a given frequency Moderate; often needs more stages Fewer stages can simplify a MIC
Breakdown / ruggedness Lower; sensitive to load mismatch and overdrive Higher; more tolerant of VSWR Bipolars need output protection and conservative derating
Noise / phase noise Strong option for low-phase-noise oscillators and LNAs Good, but device choice is narrower at the high end Depends on specific part and bias point
Thermal behavior Positive temperature coefficient of current can invite thermal runaway Self-limiting in many designs Bipolar bias must include emitter resistance or active compensation
Typical sweet spot Low-noise front ends, oscillators, driver and medium-power stages High-power amplifiers, especially below a few GHz Match the device to the stage, not the whole chain

The practical rule: use bipolars where gain, noise, and phase noise dominate the budget; use LDMOS where power and ruggedness dominate.

Key selection parameters

  1. Frequency range and gain. Work from the vendor's S-parameters or gain-vs-frequency curve at your bias point, not from a single "typical" number. Check gain at the top of your band, where it is lowest.
  2. Output power and compression point. Select for P1dB and saturated power with margin over the required output, then confirm the gain at that drive level.
  3. Breakdown voltage and safe operating area. Verify VCEO and VCBO against your supply and expected load mismatch. A mismatched load can double the voltage swing at the collector.
  4. Bias current and thermal resistance. Get Rth(j-c) or Rth(j-ambient) for the die or package, compute junction temperature at worst-case ambient, and derate. For bare die, include the die-attach and carrier in the thermal path.
  5. Noise figure (for LNAs) and phase noise (for oscillators). These are bias-dependent; specify the bias point at which the number was measured.
  6. Input/output impedance and matching. Confirm the reference plane and whether the data is for the die or the packaged part. Die-level data is what you need for a MIC.

Matching and biasing in amplifier and MIC designs

Matching

  • Input match usually needs a conjugate match at the design frequency; for broadband LNAs, trade gain flatness and noise figure against return loss.
  • Output match should be designed for the load at the collector, with harmonic termination if efficiency matters.
  • Bias network as part of the match. The bias tee or collector feed is not neutral — its inductance and bypass capacitors shift the match. Simulate the bias network with the device, not after it.
  • Use the vendor's capacitor and inductor families consistently. For example, US Microwaves lists spiral chip inductors (LX/LXT series, including high-Q and multi-tap tuning types) and silicon MIS/MNOS/MOS, ceramic, and quartz capacitors, plus thin-film resistors. Choosing parts from one characterized family reduces surprises between simulation and hardware.

Biasing

  • Current-source or resistor bias with emitter degeneration. Emitter resistance stabilizes bias against beta spread and temperature; too much costs gain and adds noise.
  • Temperature compensation. Use a diode or transistor sensor in the bias network, or active bias, to hold collector current over temperature.
  • Sequencing and protection. Apply bias in a controlled order, limit current during turn-on, and protect against load mismatch and ESD. Bipolars are less forgiving than LDMOS here.

Where bipolars are the better choice

  • Low-noise amplifier first stages where noise figure and gain per stage matter more than raw power.
  • Oscillators and low-phase-noise sources.
  • Driver and medium-power stages in hybrid MICs where a compact, well-modeled die is preferred.
  • Designs already built around a characterized bipolar die and matching library, where re-qualifying an LDMOS would add cost and schedule.

Where LDMOS or FETs usually win: high-power output stages, applications with severe load mismatch, and designs where simple voltage bias and ruggedness outweigh gain-per-stage.

Common failure modes and design checks

  • Thermal runaway. Check junction temperature at maximum ambient and worst-case bias; verify emitter resistance or active bias limits current rise.
  • Load mismatch overvoltage. Evaluate collector voltage at the worst expected VSWR; add output protection or derate.
  • Bias network instability. Bipolars can oscillate with inductive bias feeds or inadequate bypassing; check low-frequency stability, not just in-band.
  • Beta spread and lot variation. Design bias for the specified min/max beta, and verify gain across that spread.
  • Die-attach and wire-bond parasitics. For bare die, include bond-wire inductance and attach thermal resistance in the model; these often dominate at microwave frequencies.
  • Reference-plane errors. Confirm whether S-parameters are de-embedded to the die or include package and fixture; a mismatch here invalidates the match.

Practical next step

Start from the stage requirements — frequency band, gain, output power, noise or phase-noise target, and thermal budget — then shortlist bipolar parts whose data covers that band at your bias point. Request S-parameters and thermal data at the die level, build the bias network into the matching simulation, and verify junction temperature and mismatch tolerance before layout. US Microwaves' site provides product listings and a quote/cross-reference path for its RF power transistors and thin-film component families; use those listings to confirm which parts and matching components are available for your MIC.