What Is a PCIe Lane Map and How Do You Read One?
Updated
A PCIe lane map is a diagram of where every PCIe lane on a motherboard comes from and where it goes — which slots are wired directly to the CPU, which run through the chipset, how many lanes each slot gets, and which slots share lanes with each other. You read one by tracing each slot back to its source (CPU or chipset), noting the lane count and PCIe generation, then checking for shared lanes that drop bandwidth when two slots are populated at once. You need this before buying a board if your build combines a GPU, multiple NVMe drives, or expansion cards, because lane sharing can silently cut your GPU from x16 to x8 or split an M.2 slot's bandwidth.
The two lane sources: CPU-direct vs chipset
Every slot on a board traces back to one of two places.
CPU-direct lanes are the fastest and most predictable. As MoboMaps' PCIe Basics section puts it, CPUs provide roughly 20–24 usable PCIe lanes. The typical split is 16 lanes for the primary graphics slot plus 4 lanes for the first M.2 slot — 20 lanes minimum for a standard build. These lanes don't compete with chipset devices.
Chipset lanes expand connectivity beyond what the CPU offers. Extra M.2 slots, secondary PCIe slots, USB4 controllers, and network cards hang off the chipset. They share the chipset's uplink to the CPU, so heavy simultaneous use across chipset devices can contend for that link.
On a lane map, you'll see this distinction labeled directly. In the MoboMaps example for the ASUS ROG Crosshair X870E Hero (X870E, AM5, ATX), the map reads:
| Slot | Source | Generation | Lanes |
|---|---|---|---|
| PCIEX16_1 | CPU | Gen5 | x16 |
| M.2_1 | CPU | Gen5 | x4 |
| M.2_2 | CPU | Gen4 | x4 |
| PCIEX16_2 | X870E chipset | Gen4 | x4 |
| M.2_3 | X870E chipset | Gen4 | x4 |
| M.2_4 | X870E chipset | Gen4 | x4 |
| PCIEX1 | X870E chipset | Gen3 | x1 |
The pattern is common: the top x16 slot and first M.2 come straight from the CPU, everything else routes through the chipset.
Reading slot labels: lane count and generation
Slot labels tell you two things — how many lanes (x1, x4, x8, x16) and which PCIe generation (Gen3, Gen4, Gen5). Both matter for bandwidth.
Lane count sets the width of the pathway. A x16 slot has 16 lanes; a x4 slot has 4. More lanes means more bandwidth, which is why GPUs want x16 and NVMe drives typically use x4.
Generation sets the speed per lane. Each generation roughly doubles per-lane bandwidth over the previous one, so a Gen4 x4 slot moves about twice the data of a Gen3 x4 slot. A Gen5 x4 M.2 slot is faster still.
The practical takeaway: a Gen4 x4 M.2 slot and a Gen5 x4 M.2 slot have the same lane count but different ceilings. When you read a lane map, check both numbers — a slot labeled "Gen4 x4" is not the same as "Gen5 x4" even though both are x4.
Tracing lanes from source to slot
Reading a lane map means following each slot back to its origin and confirming the path makes sense for your parts.
- Find your GPU slot. It's usually the top x16 slot, CPU-direct, Gen4 or Gen5. Confirm it's x16 and not shared in a way that drops it.
- Find your primary NVMe slot. Typically CPU-direct x4, Gen4 or Gen5. This is your fastest storage path.
- List every additional slot you plan to populate — second M.2, capture card, network card, second GPU.
- Trace each one to its source. Chipset slots are fine for most add-in cards; just know they share the chipset uplink.
- Check for shared lanes on any slot you're filling (next section).
MoboMaps describes this as tracing "every lane from source to slot" so you can "see exactly how PCIe lanes route from CPU and chipset to every PCIe and M.2 slot."
Spotting lane sharing and bandwidth conflicts
Lane sharing is when two or more slots use the same physical lanes. Populate one, and the other loses bandwidth — or the shared slot itself drops to fewer lanes.
MoboMaps gives two concrete examples of how this shows up:
- GPU drops from x16 to x8. Installing an NVMe drive in a shared M.2 slot can cut the graphics slot's lanes in half. The GPU still works, but with half the bandwidth.
- M.2 shares with USB4. In the Crosshair X870E Hero example, the performance checker flags "M.2_3 shares lanes with USB4" — a bandwidth conflict detected when both are in use.
The site frames this as a design trade-off: manufacturers route lanes to give you more slots, but not all slots can run at full speed simultaneously.
To catch conflicts, toggle the devices you plan to install and watch which slots change state. MoboMaps' checker shows slots as OK, Empty, or Shared, and surfaces a conflict count — "1 bandwidth conflict detected" in the example above. The goal, as the site puts it, is to "catch conflicts before you buy — not after you build."
A concrete conflict scenario
Say you want a Gen5 GPU in the top slot, two Gen4 NVMe drives, and a USB4 device. On a board where M.2_3 shares lanes with the USB4 controller, running both means one of them loses bandwidth. The lane map shows this before you order parts — you'd either move the second NVMe to a non-shared M.2 slot or accept the trade-off.
Using a lane map before you buy
A lane map answers one question: does my exact combination of parts fit without unexpected bandwidth loss?
Check these before committing to a board:
- GPU slot stays x16 with your storage and add-in cards installed.
- Primary M.2 is CPU-direct and runs at the generation you paid for.
- Every additional M.2 you'll populate is either non-shared or shares with something you won't use.
- Chipset uplink isn't oversubscribed by too many high-bandwidth chipset devices at once.
MoboMaps maps 217 boards and offers side-by-side comparison — stacking two boards to compare specs like M.2 slot count, PCIe x16 slots, USB4 ports, and power stages at a glance. In its example, the Crosshair X870E Hero (18 power stages, 5 M.2 slots, 2 USB4, $699) sits next to the ASRock X870E Taichi (24 power stages, 4 M.2 slots, 2 USB4, $499). Comparing lane maps side by side shows which board routes lanes the way your build needs.
The site describes itself as free, forever, with no pricing signals for paid tiers in the available material. It also lists a live YouTube Q&A for motherboard questions, which is a support channel rather than a product feature.
Quick reference
| Term | What it means |
|---|---|
| CPU-direct lane | Lane wired straight from the CPU; fastest, not shared with chipset devices |
| Chipset lane | Lane routed through the chipset; shares the chipset uplink |
| x1/x4/x8/x16 | Lane count — the width of the pathway |
| Gen3/Gen4/Gen5 | PCIe generation — the speed per lane |
| Lane sharing | Two slots using the same lanes; populating one affects the other |
| Bandwidth conflict | A detected case where populating slots together reduces performance |