Why Berkeley Architecture Research Uses RISC-V and Chisel

Berkeley Architecture Research (BAR) uses RISC-V and Chisel because both were developed at Berkeley, and the group states that all of its recent microprocessor designs are based on the RISC-V instruction set and implemented with the Chisel hardware description language. This choice fits a long-standing emphasis on building working prototypes rather than only simulating designs. The same approach is relevant if you are evaluating the group's projects, reusing its open tools, or studying how architecture research moves from idea to silicon.

The two tools and where they come from

RISC-V is an open instruction set architecture; Chisel is a hardware description language. According to the BAR homepage, both were developed at Berkeley. That shared origin matters for a research group: the instruction set and the design language are not external dependencies chosen late in a project, but local infrastructure the group can extend and teach.

The page also notes that recent microprocessor designs have been taped out in advanced processes every year. In other words, RISC-V and Chisel are not just academic exercises at BAR; they are the route to fabricated chips.

Why this pairing makes sense for BAR

A tradition of prototypes

The homepage traces Berkeley computer architecture research back to the CALDIC computer completed in 1951, and lists later projects including Project Genie, RISC-I, RISC-II, SOAR, SPUR, RAID, VLSI-BAM, T0, NOW, IRAM, and RAMP. The stated continuity is explicit: Berkeley architecture research "has always emphasized construction of prototypes." RISC-V and Chisel are the current expression of that habit.

Research, teaching, and open ecosystems reinforce each other

Because both tools originated at Berkeley, using them keeps design work close to the people and courses that develop them. It also means the group's output can feed the broader open ecosystem around RISC-V and Chisel, while feedback from real tapeouts can inform the tools. The page does not detail licensing or governance, so treat the "open" characterization as general knowledge about RISC-V and Chisel rather than a claim taken from this page.

What this means if you are looking at BAR's work

• If you want to understand a BAR chip project, expect RISC-V and Chisel to be the baseline. Designs built on other instruction sets or HDLs would be the exception, not the norm, for recent work.
• If you want to reuse or learn from the group's methods, the relevant entry points are the RISC-V ISA and Chisel, plus the project links the homepage points to at the top right.
• If you are comparing research groups, a useful dimension is whether they build and tape out prototypes or mainly simulate. BAR's page makes prototype construction a defining feature, with multiple tapeouts per year in advanced processes.

Where to go next

The homepage directs readers to links at the top right for current work, and notes that BAR hosts weekly seminars on computer architecture topics, with more information at a linked page. The page also credits sponsors including DARPA, NSF, DoE, ONR, Intel, Google, and TSMC, among others—useful context if you are checking who supports this line of research.