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What is Berkeley Architecture Research?
Berkeley Architecture Research is the computer architecture research group in UC Berkeley's EECS department, presented through its homepage at Berkeley Architecture Research. The page describes a long line of processor and systems projects—from the 1951 CALDIC computer through Project Genie, RISC-I and RISC-II, RAID, NOW, and RAMP—and says the group continues to build prototype chips, with multiple microprocessor tapeouts in advanced processes each year. Recent designs use the RISC-V instruction set and the Chisel hardware description language, both developed at Berkeley. The group also runs a weekly seminar on architecture topics and lists sponsors including DARPA, NSF, Intel, Google, NVIDIA, Samsung, and TSMC.
Who it is useful for
- Prospective graduate students and researchers scouting a lab with a prototype-building tradition and RISC-V/Chisel work.
- Engineers and academics who want to follow Berkeley's chip designs and seminar topics.
- Sponsors and collaborators checking the group's project history and funding relationships.
How to use it
Start with the project links in the top-right navigation to see current work, then check the seminar page if you want to attend or follow talks. As a decision criterion: if your interest is RISC-V processor implementation or hardware description languages, this group's output is directly relevant; if you need software-only systems work, look at the specific project pages before assuming a fit.
How can I attend or follow the weekly BAR seminars?
The page lists a weekly BAR seminar series on computer architecture topics but does not itself publish the schedule, location or joining details. The page says to "Learn more at this link," so the practical route is to follow that seminar link from the Berkeley Architecture Research homepage, where the current meeting details should be posted.
What to expect and how to prepare
- Format: The page describes the series as weekly and tied to computer architecture research, so expect research talks rather than introductory lectures.
- Audience: It suits graduate students, researchers and industry engineers following processor design, hardware description languages and prototyping work.
- Context to bring: Recent Berkeley designs use RISC-V and Chisel, both developed at Berkeley, so familiarity with those helps you follow talks in that vein.
- If details are missing: Check the seminar link first; if it is not current, look for the group's announcements through the UC Berkeley EECS department or the Berkeley Architecture Research pages.
As a next step, open the seminar link on the homepage and note the day, time and whether attendance is in person or remote before planning around it.
Which past Berkeley computer architecture projects shaped today's research?
The page names a lineage of Berkeley computer architecture projects that led to today's work: Project Genie, RISC-I, RISC-II, SOAR, SPUR, RAID, VLSI-BAM, T0, NOW, IRAM and RAMP, with the department's history traced back to the CALDIC computer completed in 1951. These are the projects the page itself presents as the predecessors of current research, so they are the best starting list for anyone tracing how Berkeley's approach developed.
What each strand contributes to current work
The page does not describe each project in detail, so the following groups them by the theme the page emphasizes rather than by individual claims:
- Instruction set and processor design — RISC-I and RISC-II sit at the root of the reduced instruction set approach. The page notes that all recent Berkeley microprocessor designs use RISC-V, also developed at Berkeley, making this the most direct line from past to present.
- Prototype-driven hardware — The page states that Berkeley architecture research "has always emphasized construction of prototypes," continuing today with multiple microprocessor tapeouts in advanced processes each year. Projects such as SOAR, SPUR and IRAM belong to this building-and-testing tradition.
- Design methodology and tooling — Recent designs are implemented in Chisel, a hardware description language developed at Berkeley. This reflects a long-standing interest in how chips are specified and generated, not only what they compute.
- Parallel and networked systems — NOW (network of workstations) and RAID point to Berkeley's role in rethinking how storage and computing are organized across many machines, a concern that recurs in today's accelerator and datacenter research.
How to use this
If you are deciding where to read first, pick by interest rather than chronology. Someone evaluating a RISC-V-based design should start with RISC-I and RISC-II and then look at current tapeouts; someone interested in research infrastructure should look at NOW, RAID and RAMP. The page also notes a weekly BAR seminar on computer architecture topics, which is the practical way to see which of these threads are active now. For broader context on the lab's current projects, see Berkeley Architecture Research.
What role does RISC-V play in Berkeley's current microprocessor designs?
RISC-V serves as the instruction set basis for all of Berkeley's recent microprocessor designs. According to the Berkeley Architecture Research group, every recent chip design is built on RISC-V, and those designs are implemented in Chisel, the hardware description language also developed at Berkeley.
What this means in practice
- RISC-V is the instruction set architecture (ISA) — the contract between software and hardware. Choosing it means the group's prototypes run a shared, open instruction set rather than a proprietary one, so code and tooling can be reused across designs.
- Chisel is the implementation layer — designs are written in Chisel and then generated into hardware, which fits the group's emphasis on building working prototypes rather than only simulations.
- Prototypes are the output — the group describes multiple microprocessor tapeouts in advanced processes every year. RISC-V is the common thread across those chips.
Why the pairing matters
An open ISA lowers the barrier to experimenting with new microarchitectural ideas: a research team can change how a processor is built without renegotiating a license or rewriting software from scratch. Chisel adds a further layer of reuse, since parameterized designs can be generated for different configurations.
This makes the work most relevant to readers interested in processor research, open instruction sets, or hardware design languages — for example, a graduate student who wants to understand how a research chip goes from idea to silicon would look at the RISC-V and Chisel combination as the starting toolkit.
A useful next step
If you want to see how these ideas appear in actual chips, look for the group's published tapeout results and seminar topics, which the site points to through its weekly BAR seminar series. For broader context on the open ISA ecosystem, RISC-V International documents the specification and community around it.
Why does Berkeley emphasize building prototype chips and tapeouts?
Berkeley's architecture group treats building real chips as the core of its research method, not as a demonstration tacked onto the end. The page frames this as a long-standing tradition: from the CALDIC computer in 1951 through Project Genie, RISC-I and RISC-II, SOAR, SPUR, RAID, NOW, IRAM and RAMP, and continuing today with multiple microprocessor tapeouts in advanced processes each year. The stated emphasis is on "construction of prototypes," and recent designs are built on RISC-V with the Chisel hardware description language, both developed at Berkeley.
Why prototypes rather than simulation alone
A tapeout forces the questions that paper designs can defer. Once a chip must be fabricated, timing, power, area and physical integration stop being assumptions and become constraints someone has to meet. That pressure tends to expose whether an architectural idea survives contact with a real process, and it produces artifacts—working silicon, tooling, and open instruction-set and language infrastructure—that other researchers can build on rather than re-derive. The page also notes the breadth of sponsorship (DARPA, NSF, DoE, ONR, Intel, Google, NVIDIA, Samsung, TSMC and others), which fits an approach where fabrication costs and multi-year effort require institutional backing.
Who benefits, and the trade-off
- Graduate students and postdocs gain experience across the full flow, from microarchitecture to physical design and bring-up—skills that simulation-only projects rarely teach.
- Industry and academic collaborators get validated designs and shared infrastructure (RISC-V, Chisel) they can adopt or critique.
- The research community gets evidence that an idea works in silicon, which is harder to dispute than a model.
The cost is real: tapeouts are slow, expensive and risky, and a failed chip can consume a funding cycle. Groups without fabrication access or sponsor support are better served by FPGA prototypes or simulation, accepting weaker evidence in exchange for speed and lower cost.
For a concrete case: a student weighing a thesis topic can use the distinction as a decision rule—if the claim is about physical efficiency or integration, plan for silicon or at least an FPGA prototype; if it is about a scheduling policy or ISA semantics, a rigorous simulator study may answer the question faster. The group's weekly BAR seminars are one way to see how current projects handle that trade-off.
Who sponsors Berkeley Architecture Research and how does sponsorship support the work?
Berkeley Architecture Research lists its sponsors as DARPA, NSF, DoE, ONR, C-FAR, Intel, Google, HP, Huawei, IBM, LGE, Microsoft, National Instruments, NEC, Nokia, NVIDIA, Oracle, Samsung, ST Microelectronics, TSMC, and Xilinx. The mix is telling: government and defense research agencies alongside semiconductor, systems and consumer-electronics companies.
How sponsorship supports the work
The page describes a research culture built on making real hardware, not just simulations: the group says it has emphasized prototype construction throughout its history, and that this continues with "multiple microprocessor tapeouts in advanced processes every year." Sponsorship is what makes that kind of work possible. Tapeouts—fabricating actual chips—are among the most expensive and resource-intensive activities in academic computer architecture, requiring access to advanced manufacturing processes and design tooling. Industry sponsors such as TSMC and the EDA and systems vendors on the list are the natural source of that access; agencies like DARPA, NSF, DoE and ONR typically fund the research agenda, students and long-horizon exploration.
The page also frames sponsorship as enabling continuity. It thanks "the long list of past and present sponsors," which fits a program whose projects span decades—from CALDIC in 1951 through Project Genie, RISC-I and RISC-II, SOAR, SPUR, RAID, NOW, IRAM and RAMP, to today's RISC-V and Chisel-based designs. Sustained funding across that arc is what lets one project's tools and lessons feed the next.
What this means in practice
If you are evaluating the group—say, as a prospective graduate student or an industry collaborator—the sponsor list is a useful signal of where the work sits: close to real silicon and to the companies that build it. A practical next step is to look at the current project pages linked from the site and match them to the sponsors whose interests align, since that pairing usually indicates which problems are being pushed toward fabrication. For broader context on the RISC-V ecosystem the group helped create, see RISC-V International.
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